Key Takeaways
- Moore’s Law is no longer delivering the historic 50 % yearly density gains; scaling has become linear since ~2010, but innovation continues through new transistor architectures and packaging.
- IMEC’s roadmap projects the first sub‑1 nm logic node (A7, ~0.7 nm) based on Complementary FETs (CFETs) to appear around 2034, followed by A5 (0.5 nm) by 2036 and A3 (0.3 nm) by 2040.
- Beyond 2040, the industry will explore 2‑D FET technologies, targeting an A2 (0.2 nm) node by 2043 and sub‑0.2 nm solutions by 2046, leveraging materials such as epitaxial PtCoO₂ on sapphire.
- Back‑End‑of‑Line (BEOL) interconnects will evolve from copper dual‑damascene to ruthenium‑based semi‑damascene processes, introducing air gaps and self‑aligned vias to cut resistance and enable ultra‑tight metal pitches down to ~12 nm for the deepest nodes.
- Integrated Voltage Regulators (IVRs) are slated to move from the motherboard PCB into the package itself by 2028‑2032, using 2.5‑D MIM capacitors and through‑silicon vias to deliver tighter power delivery for AI and HPC workloads.
- Advanced packaging (chiplets, 2.5D/3D stacking, TSMC’s SoW, Intel’s EMIB/T) remains a critical lever for performance gains while the economics of pushing ever‑smaller process nodes become prohibitive.
- Overall, the roadmap underscores that while traditional scaling slows, a combination of novel transistor designs, new materials, 3‑D integration, and smarter power management will sustain density, performance, and efficiency improvements for decades to come.
The Slowing of Traditional Moore’s Law Scaling
For many years, transistor density doubled roughly every two years, driven by aggressive lithography and device scaling. IMEC’s data shows that from 1998 to 2010, logic density increased at about 50 % per year, effectively halving SRAM cell area annually. After 2010, however, the rate dropped to a near‑linear trend, meaning that each new node delivers only modest density improvements. This slowdown reflects the growing physical and economic challenges of pushing silicon‑based geometries to their limits, including escalating fab costs, heightened variability, and power‑density concerns. Consequently, the industry has begun to rely more heavily on architectural tricks and advanced packaging rather than pure node shrinkage to sustain performance growth.
The Rise of Nanosheet FETs and Gate‑All‑Around Architecture
The next step beyond the FinFET era is the adoption of nanosheet (or gate‑all‑around, GAA) transistors. TSMC’s N2 node, slated for production in 2025, marks the first commercial deployment of this architecture, with follow‑up nodes such as A16, A14, A13, and A12 arriving shortly thereafter. Intel is also pursuing its own nanosheet family, labeled 14A and its derivatives. These GAA nanosheets provide better electrostatic control, reduced leakage, and a path toward higher density compared with FinFETs. IMEC’s roadmap indicates that nanosheet‑based scaling will continue through roughly 2031, with the A10 node representing the last major nanosheet generation before the transition to truly sub‑1 nm technologies.
Entering the Sub‑1 nm Era with Complementary FETs (CFETs)
Once nanosheet scaling nears its practical limits, the roadmap calls for Complementary FETs, where p‑type and n‑type nanosheet sheets are stacked vertically. This vertical integration cuts the cell footprint dramatically, delivering an estimated 1.6‑ to 1.8‑fold density gain over a single‑layer nanosheet layout. The first CFET node, designated A7 (~0.7 nm), is projected for completion around 2034, with subsequent refinements leading to A5 (~0.5 nm) by 2036 and A3 (~0.3 nm) by 2040. IMEC notes that continued improvements in CFET design could push CMOS logic density up by as much as 80 % relative to today’s most advanced nodes, providing the raw transistor count needed for future AI, high‑performance computing, and emerging workloads.
Beyond CFETs: The Advent of 2‑D FET Technologies
Looking further ahead, the roadmap anticipates a shift to two‑dimensional (2‑D) channel materials once CFET scaling reaches its intrinsic limits. By 2043, an A2 node (~0.2 nm) is expected to debut the first 2‑D FETs, replacing traditional silicon nanosheets with atomically thin layers such as transition‑metal dichalcogenides or graphene derivatives. These materials promise exceptional carrier mobility and ultra‑thin bodies, enabling further reductions in device dimensions. A subsequent sub‑A2 (<0.2 nm) generation is slated for 2046, representing the ultimate miniaturization target in the IMEC vision. While these dates are speculative and contingent on breakthroughs in material synthesis, defect control, and integration, they illustrate the industry’s long‑term commitment to pushing the boundaries of what a transistor can be.
BEOL Interconnect Evolution: From Copper to Ruthenium and Beyond
Scaling the transistors themselves is only half the story; the wiring that connects them must keep pace. Today’s BEOL relies on copper dual‑damascene or single‑damascene processes with a metal pitch of roughly 24‑26 nm. IMEC’s roadmap shows a gradual pitch reduction to 20‑22 nm by the A14 node (2028) and then a transition to semi‑damascene (subtractive) methods that incorporate ruthenium (Ru). Ru enables the formation of intentional air gaps and self‑aligned vias, which lower resistance and reduce wasted volume. For the deepest nodes (A5/A3 and beyond), the roadmap proposes alternate conductive materials such as epitaxial PtCoO₂ on sapphire, promising pitches as low as 12‑16 nm. These BEOL advances are essential to mitigate RC delay and power loss as transistor density climbs.
Power Delivery Innovation: Moving Integrated Voltage Regulators On‑Package
As compute density rises, delivering clean, low‑voltage power to billions of transistors becomes a bottleneck. The roadmap outlines a plan to migrate Integrated Voltage Regulators (IVRs) from the motherboard PCB into the package itself by 2028‑2032. These on‑package IVRs would step down standard 48 V DC rails to intermediate voltages (≈12 V) and finally to the sub‑1 V levels required by modern logic. Implementation leverages 2.5‑D metal‑in‑metal (MIM) capacitors, through‑silicon vias (TSVs), and emerging “Can/SI” power devices. Intel’s EMIB/T technology already demonstrates how power can be routed through TSVs to logic dice, and the roadmap extends this concept to broader adoption. By placing regulation closer to the compute die, designers can reduce IR drop, improve dynamic response, and support the tight power envelopes demanded by AI accelerators and high‑performance cores.
The Role of Advanced Packaging and Chiplets in Sustaining Growth
Even as transistor scaling slows, the semiconductor industry continues to extract performance gains through heterogeneous integration. Chiplet‑based designs, 2.5D/3D stacking, and technologies such as TSMC’s System‑on‑Wafer (SoW) and Intel’s EMIB/T enable designers to mix and match dies fabricated on different nodes, optimize power‑performance trade‑offs, and improve yield. The roadmap emphasizes that reliance on these packaging strategies has reduced the immediate pressure to migrate to the very latest process nodes, offering a cost‑effective path to higher system‑level density. Moreover, advanced packaging facilitates tighter coupling between compute logic and memory (including HBM and emerging DRAM technologies), which is crucial for bandwidth‑intensive AI workloads. In essence, while the raw transistor pitch may advance more slowly, the overall system can still scale through smarter architectural integration.
Conclusion: A Multifaceted Path Forward
IMEC’s detailed roadmap makes clear that the era of relentless, geometry‑only scaling is over, but innovation is far from stagnant. The combination of nanosheet FETs, CFETs, and eventually 2‑D FETs will continue to push the intrinsic limits of the transistor itself. Simultaneously, breakthroughs in BEOL materials—ruthenium air gaps, exotic conductive oxides, and ultra‑tight pitches—will preserve signal integrity as interconnects grow denser. On the power side, moving voltage regulation onto the package and adopting advanced capacitive and TSV‑based delivery methods will keep energy efficiency in step with rising computational demand. Finally, advanced packaging and chiplet approaches provide a pragmatic, cost‑aware mechanism to reap the benefits of both cutting‑edge and mature process nodes. Together, these strands form a robust framework that should sustain performance, efficiency, and functionality gains for AI, high‑performance computing, and the next generation of electronic devices well into the 2040s and beyond.