Key Takeaways
- Google is reportedly collaborating with AMD on the development of its 10th‑generation TPU (TPU v10).
- Analysts at SemiAnalysis suggest AMD may contribute CPU IP, advanced packaging expertise, or hybrid‑design know‑how rather than designing a conventional TPU.
- The partnership could yield a TPU variant that integrates on‑package CPU cores to better serve reinforcement‑learning (RL) and agentic‑model workloads.
- Google’s recent TPU 8i inference systems already pair one Axion CPU with every two TPUs, indicating a trend toward tighter CPU‑accelerator coupling.
- If the rumor holds true, AMD would mark its first major involvement in a custom AI ASIC project, leveraging its experience with the Instinct MI300A hybrid x86‑accelerator design.
Background on Google’s TPU Evolution
Google has released nine generations of its proprietary Tensor Processing Units (TPUs), with Broadcom handling the actual silicon design for most of them. “Having developed nine generations of its proprietary AI accelerators … Google hardly needs AMD to design a conventional TPU,” the SemiAnalysis note observes. This history underscores that any AMD contribution would likely be specialized rather than a full‑scale TPU redesign. The company’s TPU line has steadily increased performance for large‑language‑model (LLM) training, but emerging workloads are shifting the balance toward more general‑purpose compute.
Why AMD Might Be Involved
SemiAnalysis analysts argue that Google’s interest in AMD stems from the chipmaker’s strengths in CPU IP, advanced packaging, and system‑on‑chip (SoC) integration. “AMD has strong IP, especially in advanced packaging and SoIC. Additionally, CPU IP could also be a draw given Google and its customers are pushing for TPUs with on‑package CPU cores for RL workloads,” the note states. Rather than asking AMD to fabricate another TPU core, Google may be seeking AMD’s expertise to embed x86 cores directly alongside its tensor accelerators, creating a heterogeneous AI package.
The Reinforcement‑Learning Angle
Reinforcement learning (RL) and agentic models often demand substantial general‑purpose compute to orchestrate policy searches, simulation environments, and complex control loops—tasks that are less suited to pure tensor cores. SemiAnalysis notes, “Google and its customers are pushing for TPUs with on‑package CPU cores for reinforcement learning and potentially other CPU‑heavy workloads.” By integrating CPU cores within the TPU package, Google could reduce latency and power overhead associated with moving data between separate CPU and accelerator sockets, a critical factor for iterative RL algorithms.
Current CPU‑TPU Ratios in Google’s Infrastructure
Google’s latest inference‑oriented TPU 8i systems already reflect a move toward tighter CPU integration: they feature one Google‑designed Axion CPU for every two TPUs. In contrast, the previous generation’s servers paired a single Intel Xeon “Emerald Rapid” processor with four TPUs. The article mentions, “Furthermore, we are hearing that in some cases a 1:1 ratio of CPUs to accelerators is optimal, so the future of AI may be way more CPU‑heavy than we think.” This trend suggests that future TPU designs may need to accommodate more on‑die or on‑package CPU resources to meet performance targets.
AMD’s Hybrid Design Pedigree
AMD’s experience with the Instinct MI300A—a data‑center GPU that couples x86 CPU cores, GPU compute units, and high‑bandwidth memory (HBM) in a single package—provides a relevant blueprint. “AMD already has experience developing a data‑center‑grade design — the Instinct MI300A — that packs both x86 and accelerator chiplets,” the analysis points out. A hypothetical Google TPU v10 could thus combine Google‑made TPU compute chiplets with AMD CPU chiplets and HBM, all assembled using AMD’s advanced packaging techniques such as chip‑on‑wafer‑on‑substrate (CoWoS) or silicon‑interconnect fabric (SiIF).
Alternative Partners and Strategic Considerations
While Intel has a longstanding relationship with Google, the note highlights a potential limitation: “Intel has no experience building hybrid x86+accelerator data center designs.” This gap makes AMD a more attractive collaborator for a project that requires tight integration of CPU and accelerator silicon. Nevertheless, the analysis cautions that the current information is speculative: “Note that for now we are speculating and our analysis may be inaccurate.” Any concrete details about the scope of AMD’s involvement—whether it supplies CPU cores, packaging technology, or interconnect IP—remain unconfirmed.
Implications for the AI Hardware Landscape
If Google proceeds with a CPU‑heavy TPU v10 variant, it could signal a broader industry shift toward heterogeneous AI accelerators that blend specialized tensor cores with general‑purpose processors. Such designs may improve efficiency for workloads where control logic, data preprocessing, or environment simulation constitute a non‑trivial fraction of total compute time. Moreover, AMD’s first major role in a custom AI ASIC would bolster its position in the data‑center AI market, potentially opening doors for further collaborations with other hyperscalers seeking customized silicon solutions.
Conclusion and Outlook
The SemiAnalysis‑cited rumor paints a picture of Google exploring a new direction for its TPU family—one that leverages AMD’s CPU and packaging expertise to better serve reinforcement‑learning and agentic AI tasks. While the exact nature of AMD’s contribution remains uncertain, the potential partnership underscores the evolving balance between accelerator‑centric and CPU‑centric compute in modern AI infrastructure. As the industry continues to push the limits of model size and complexity, hybrid designs that place CPU cores ever closer to tensor cores may become a defining feature of next‑generation AI hardware.
Journalistic note: All quoted passages above are drawn directly from the SemiAnalysis client note referenced in the original Tom’s Hardware article.
https://www.tomshardware.com/tech-industry/artificial-intelligence/google-reportedly-taps-amd-to-design-next-generation-tpu-hybrid-ai-asic-could-integrate-on-package-cpu-cores-for-reinforcement-learning