Key Takeaways
- Huawei unveiled an updated AI hardware roadmap at Huawei Connect, accelerating the Ascend 960 series and disclosing specs for the forthcoming Ascend 970 and 980 accelerators.
- The company is transitioning from legacy SIMD‑only designs to a new SIMD + SIMT architecture (dubbed Peerium) that combines vector processing with thread‑level parallelism for better utilization across diverse AI workloads.
- Ascend 950PR and 950DT NPUs are the first products to adopt the new architecture, with the Atlas 950 SuperPoD already seeing limited commercial deployment despite production‑capacity constraints.
- Ascend 960DT is slated for Q1 2027 (three quarters earlier than planned), delivering 2 FP8 PFLOPS and 4 FP4 PFLOPS, 288 GB of HiZQ memory at 9.6 TB/s bandwidth, and a 2.2‑TB/s interconnect.
- Ascend 960PR follows in Q3 2027, offering 2 FP8 PFLOPS for training and a doubled 8 FP4 PFLOPS for inference, reflecting a substantial rework of low‑precision compute capabilities.
- Looking ahead, Ascend 970 (2028) and Ascend 980 (2029) are projected to roughly double compute performance each generation, with the 980 targeting 7.2 FP8 PFLOPS, 28 FP4 PFLOPS, 384 GB memory, 38.4 TB/s bandwidth and an 8‑TB/s interconnect.
- Huawei’s roadmap maintains a one‑generation‑per‑year cadence, driven by the “Tau (τ) Scaling Law” that promises continual improvements in compute, memory bandwidth, capacity and interconnect.
- Despite aggressive timelines, the Atlas 950 SuperPoD’s rollout remains slow, likely hampered by supply constraints and the software redesign required for the new SIMD + SIMT architecture.
Overview of Huawei’s AI Hardware Roadmap Update
At its annual Huawei Connect event, Huawei refreshed its AI accelerator roadmap, pulling forward the Ascend 960 series and revealing preliminary specifications for the Ascend 970 and 980 chips. The company emphasized that it is “evolving our Ascend chip series on a one‑generation‑a‑year cycle,” as stated by David Wang, Deputy Chairman of the Board and Rotating Chairman, in his keynote. This cadence underpins the aggressive timelines for the upcoming generations, which aim to double compute performance while simultaneously boosting memory and interconnect capabilities.
Shift from SIMD to SIMD + SIMT Architecture
A central theme of the update is Huawei’s migration from the SIMD‑only designs that have powered its Ascend NPUs for nearly a decade to a hybrid SIMD + SIMT architecture. The new design, dubbed Peerium and built on the UnifiedBus, fuses vector‑based data parallelism (SIMD) with thread‑level parallelism (SIMT) to improve hardware utilization across a broader spectrum of AI workloads, particularly those with divergent control flow. As the article notes, “The first Ascend NPUs to adopt Huawei’s new architecture are Ascend 950PR for prefill and recommendation, as well as Ascend 950DT for decoding and training.”
Ascend 950 Series: First Products with Peerium
The Ascend 950PR and 950DT NPUs debuted as the initial silicon to incorporate the SIMD + SIMT approach. According to Huawei, the Atlas 950 SuperPoD systems built around these chips are already in “large‑scale commercial use,” although the company did not disclose specific customer names. Testing of the training‑focused Ascend 950DT yielded “good results,” prompting expectations that numerous Chinese AI developers will begin training models on 950DT‑based systems in the coming year. Nonetheless, Huawei admitted that “its production capacity remains insufficient to satisfy domestic demand,” hinting at a bottleneck that could slow broader adoption.
Atlas 950 SuperPoD Specifications and Real‑World Deployment
In September 2025 Huawei announced the theoretical maximum configuration for the Atlas 950 SuperPoD: 2,048 Kunpeng 950 CPUs, 8,192 Ascend 950DT NPUs, 160 cabinets (128 compute + 32 communications), delivering 8 FP8 EFLOPS, 16 FP4 EFLOPS and 16 PB/s of aggregate interconnect bandwidth. By July 2026, however, a publicly shown implementation featured only 256 CPUs and 1,024 accelerator cards—far below the peak. The article observes that while Huawei still claims scalability to 8,192 NPUs, the absence of the full spec on its website leaves the actual scale of commercial deployments uncertain, suggesting that the SuperPoD is serving as a “pipecleaner” to clear the path for more capable Ascend 960‑series accelerators.
Accelerated Launch of Ascend 960DT
Huawei moved up the release of the Ascend 960DT by three quarters, targeting formal availability in Q1 2027. The accelerator is projected to deliver 2 FP8 PFLOPS and 4 FP4 PFLOPS, equipped with 288 GB of HiZQ memory offering 9.6 TB/s bandwidth and a 2.2‑TB/s interconnect. These figures represent a substantial step up from the 950 series and underscore Huawei’s commitment to pushing performance envelope while adhering to its annual cadence.
Ascend 960PR: Doubling FP4 Inference Performance
Scheduled for Q3 2027, the Ascend 960PR NPU will retain the 2 FP8 PFLOPS training capability of its DT counterpart but will double the FP4 inference performance to 8 PFLOPS—twice the figure originally forecast. The article highlights that this leap “likely means that the company has substantially reworked the processor’s low-precision compute capabilities rather than merely adjusted its memory subsystem or clock speeds.” The 960PR will also feature 192 GB of memory with 2.4 TB/s bandwidth and preserve the 2.2‑TB/s interconnect, maintaining consistency across the 960 family.
Future Outlook: Ascend 970 and Ascend 980
Looking further ahead, Huawei disclosed that the Ascend 970, slated for 2028, will provide 3.6 FP8 PFLOPS and 14 FP4 PFLOPS, backed by 288 GB of memory at 14.4 TB/s bandwidth and a 4.4‑TB/s interconnect. The Ascend 980, expected in 2029, is projected to reach 7.2 FP8 PFLOPS and 28 FP4 PFLOPS, with 384 GB of memory, 38.4 TB/s bandwidth and an 8‑TB/s interconnect. The source notes that the 980 figures are “preliminary,” but they illustrate Huawei’s ambition to continue roughly doubling compute performance each generation while simultaneously enhancing memory and interconnect specs, a trend the company attributes to the “Tau (τ) Scaling Law.”
Implications for the AI Ecosystem
By advancing its accelerator roadmap and adopting a more versatile SIMD + SIMT architecture, Huawei aims to address a wider array of AI workloads—from data‑parallel matrix operations to branch‑intensive recommendation and decoding tasks. The early availability of the 960 series could give Chinese AI developers a competitive edge in training large‑scale models, especially if production constraints are alleviated. However, the slower‑than‑expected rollout of the Atlas 950 SuperPoD suggests that software ecosystem readiness and supply‑chain challenges may temper the immediate impact of these hardware advances. As Huawei continues to iterate on its NPU designs, the industry will watch closely whether its performance promises translate into broader market adoption and how they stack up against rival offerings such as Nvidia’s upcoming VR200 GPU.
https://www.tomshardware.com/tech-industry/artificial-intelligence/huawei-details-ai-accelerator-roadmap-pulls-in-next-generation-ascend-npus-by-quarters-fp4-performance-of-the-ascend-960pr-doubles-expectations